1. Field of the Invention
The present invention relates to a power voltage driver circuit for a low power operation mode in a semiconductor memory device, and in particular to an improved power voltage driver circuit for a low power operation mode which can be stably operated, reducing power consumption in the low power operation mode.
2. Description of the Background Art
FIG. 1 is a circuit diagram illustrating a conventional power voltage driver circuit including a voltage comparing unit 1 and a driver unit 2. Referring to FIG. 1, an output signal VDLI from the voltage comparing unit 1 is transmitted as a power supply source of a clock input buffer for a memory operation. An input signal VLR of the voltage comparing unit 1 is generated in a constant voltage generating unit, and the voltage level of the input signal VLR maintains half an output signal VDLI/2 regardless of variations of an external power voltage VDD. In addition, an input signal VLNG of the voltage comparing unit 1 is generated in the constant voltage generating unit, and maintains a threshold voltage value Vtn of an NMOS transistor regardless of variations of the external power voltage VDD.
As illustrated in FIG. 1, the voltage comparing unit 1 and the driver unit 2 are formed as a type of current mirror, and include: PMOS transistors P1 and P2 for constantly supplying the power voltage VDD to nodes Nd1 and Nd2; NMOS transistors N1 and N2 for receiving the input signal VLR and a signal of a node Nd5, and determining the potentials at the nodes Nd1 and Nd2 in response to a magnitude of the signals; an NMOS transistor N3 for discharging a current transmitted to a node Nd3 through the NMOS transistors N1 and N2 to a ground voltage Vss in response to the input signal VLNG; a PMOS transistor P3 for transmitting the power voltage VDD to an output terminal Nd4 in response to the signal of the node Nd1; a PMOS transistor P4 for transmitting the signal of the output terminal node Nd4 to the node Nd5 in response to the signal of the node Nd5; and a PMOS transistor P5 connected in a diode structure between the node Nd5 and the ground voltage Vss.
When the power voltage driver circuit receives the input signals VLR and VLNG from the constant voltage generating unit, the power voltage driver circuit outputs the signal VDLI obtained by stepping down the power voltage VDD to the output terminal Nd4 through the driver unit 2 by the voltage comparing unit 1 comparing and outputting the input signal VLR and the reference voltage Nd5.
FIG. 2 is a timing diagram for entrance to a deep power down (DPD) mode in a conventional semiconductor memory device, showing a precharge entrance period (a) and a DPD mode entrance period (b).
FIG. 3 is a timing diagram for extrication from the DPD mode showing a DPD mode extrication period (c), a mode bank precharge entrance period (d) and an auto refresh entrance period (e).
The conventional semiconductor memory device uses the DPD mode to reduce power consumption during non-operation. As shown in FIG. 2, when input pins of a clock signal CKE, a chip selector signal /CS, a RAS bar signal /RAS, a CAS bar signal /CAS and a write enable signal /WE are in low, low, high, high and low states, respectively, the semiconductor memory device enters into the DPD mode. When entering into the DPD mode, the semiconductor memory device maintains a lower power state than when in a standby mode. In order to extricate from the DPD mode, the clock signal CKE needs to transition from a low to high state, as shown in FIG. 3.
The clock input buffer monitoring the state of the clock signal CKE must be operated in the DPD mode to extricate from the DPD mode.
FIG. 4 is a block diagram illustrating the conventional power voltage driver circuit and clock input buffer. There are shown an internal step-down power driver circuit unit 10 having the voltage comparing unit 1 and the driver unit 2, a constant voltage generating unit 3, a clock input buffer unit 4 and a data output driver unit 5.
The constant voltage generating unit 3 receives the external power voltage VDD and the ground voltage VSS, and generates constant voltages VLR and VLNG to be used as the input signals of the voltage comparing unit 1.
The voltage comparing unit 1 receives the external power voltage VDD and the ground voltage VSS, and generates a signal ENB obtained by comparing and amplifying the constant voltages VLR and VLNG from the constant voltage generating unit 3.
The driver unit 2 generates the internal step-down voltage VDLI by using the external power voltage VDD according to the output signal ENB from the voltage comparing unit 1.
The clock input buffer unit 4 is operated according to the external clock CKE by using the internal step-down voltage VDLI generated in the driver unit 2.
In FIG. 4, an external power voltage VDDQ used as a power source of the data output driver unit 5 has a lower potential value than the external power voltage VDD.
However, the conventional power voltage driver circuit has a disadvantage in that the clock input buffer unit 4 uses the internal power voltage VDLI generated in the internal step-down power driver circuit 10 as a power voltage, and thus the driver unit 2 must be operated even in a low power mode to operate the clock input buffer unit 4. That is, the driver unit 2 is operated in the low power DPD mode, thereby increasing power consumption.
Accordingly, it is an object of the present invention to provide a power voltage driver circuit for a low power operation mode which can be stably operated, reducing power consumption in the low power operation mode.
In order to achieve the above-described object of the invention, there is provided a power voltage driver circuit for a low power operation mode in a semiconductor memory device, including: a constant voltage generating unit for generating a first constant voltage and a second constant voltage; a clock input buffer unit using an internal step-down voltage as a power source; a control unit for receiving an operation control signal indicating the low power operation mode; a voltage comparing unit controlled in response to the output signal from the control unit, for stopping the operation in the low power operation mode, and receiving the first and second constant voltages in the other operation modes, and generating a signal by comparing and amplifying the first and second constant voltages with a reference voltage; and a driver unit controlled according to the output signal from the control unit and the output signal from the voltage comparing unit, for generating the internal step-down voltage by using a first external power voltage in the other operation modes, and by using a second external power voltage in the low power operation mode.
The second external power voltage has a lower potential value than the first external power voltage.
The first constant voltage maintains half an internal step-down voltage regardless of variations of the first external power voltage, and the second constant voltage maintains a threshold voltage value of an NMOS transistor regardless of variations of the first external power voltage.
The control unit includes one inverter.
The voltage comparing unit includes: a differential amplifying unit operated in response to the second constant voltage, for comparing the first constant voltage with the reference voltage, and outputting an amplified signal; and an output unit having first to fourth MOS transistors connected in series between an output terminal generating the internal step-down voltage and a ground voltage. The first and fourth MOS transistors have a diode structure, the second and third MOS transistors are controlled in response to the output signal from the control unit, and the reference voltage is outputted from a node between the second and third MOS transistors.
The first and fourth MOS transistors are PMOS transistors, and the second and third MOS transistors are NMOS transistors.
The driver unit includes: a fifth MOS transistor for supplying the first external power voltage to an output node of the differential amplifying unit in response to the output signal from the control unit; a sixth MOS transistor for supplying the second external power voltage to the output terminal outputting the internal step-down voltage in response to the output signal from the control unit; and a seventh NMOS transistor for supplying the first external power voltage to the output terminal outputting the internal step-down voltage in response to the signal of the output node of the differential amplifying unit.
The fifth to seventh MOS transistors are PMOS transistors.